Industry is so different I don't know where to start complaining.
Xilinx tools are not used for simulation usually because they suck and we generally pay those other tool vendors for their stuff so we might as well use them.
Given that newbies don't want to pay, maybe Xilinx is the best. I don't know much about the free stuff.
Looking at previous posts, there is so much behavioral code everywhere. We don't write a lot behavioral stuff in VHDL usually. There are higher level languages for behavioral code. Once again, you probably have to pay for those tools so maybe you have no good choices other that behavioral VHDL.
IF generic you are stuck with the Xilinx behavioral VHDL, I still would NOT write the behavioral stuff to be a cycle accurate representation of the design. You are just as likely to make a mistake in the behavioral as the RTL. Then when you test the behavioral model against the RTL you will spend half your time debugging the behavioral side. Thinking ahead really helps.
The whole approach is wonky from the start. If it were me I would think about the project as a whole and plan ahead. The design is complex in terms of verification. We always assume that every design is complex to verify! If not you wouldn't need HW in the first place.
There will be lots of tests. How does the test bench run a big suite of tests and report failures? You do not want to look at waveforms unless your test finds a failure. This blog jumps straight to waves!
I would start from the whole design first. Figure out the interfaces. Then try to express those interfaces in terms of transactions.
In fact, maybe don't even start writing VHDL as an expression of the design. Most times in industry we design via documents first. Docs express how the HW will work at a high level and how it will be verified. It breaks the design down into modules. It explains the interfaces between modules. These interfaces become possible points for the verification to look at. The test bench compares the simulated result with a golden reference when it sees a transaction event at the interface and reports a mismatch.
The point is create project infrastructure first via planning. Have a big picture view of how it's all going to be thoroughly tested automatically each time new code is committed. In industry on top of directed tests, we use constrained randomized tests. We have to determine whether we have covered everything. So we need functional coverage. All this is designed first BEFORE we play around with flops.
We can tolerate a lot of craptastic VHDL/Verilog code in industry because at the higher levels it looks neat and tidy and it is all tested vigorously.
Basically don't follow any stuff from academia because I would bet those guys have never delivered a commercial product. Educational material from tools guys is almost as bad for similar reasons. No one can hold your hand so you have to use your brain.
I probably vented too much here. It's just tough to see engineering done badly.
This is some great stuff, thanks for all the feedback - seriously. My VHDL experience is probably about 2/3 online tutorials, and they were all behavioural. The main aim of the articles are for me to learn.
The point about documentation is valid. However, as I've has no training at all in this, I'd be writing a document that basically has no value. After this project has come to it's conclusion, I'll probably go try again using processes/methods learned.
It's just that from my perspective, I can only focus on the future problems. I am too traumatized from the HW experience!
I almost rewrote a couple of my points again just now.:)
You are documenting via your blog in a sense. It has value. It is a high level representation of your plans for the project.
It does have a pipeline BTW.
Industry is so different I don't know where to start complaining.
Xilinx tools are not used for simulation usually because they suck and we generally pay those other tool vendors for their stuff so we might as well use them.
Given that newbies don't want to pay, maybe Xilinx is the best. I don't know much about the free stuff.
Looking at previous posts, there is so much behavioral code everywhere. We don't write a lot behavioral stuff in VHDL usually. There are higher level languages for behavioral code. Once again, you probably have to pay for those tools so maybe you have no good choices other that behavioral VHDL.
IF generic you are stuck with the Xilinx behavioral VHDL, I still would NOT write the behavioral stuff to be a cycle accurate representation of the design. You are just as likely to make a mistake in the behavioral as the RTL. Then when you test the behavioral model against the RTL you will spend half your time debugging the behavioral side. Thinking ahead really helps.
The whole approach is wonky from the start. If it were me I would think about the project as a whole and plan ahead. The design is complex in terms of verification. We always assume that every design is complex to verify! If not you wouldn't need HW in the first place.
There will be lots of tests. How does the test bench run a big suite of tests and report failures? You do not want to look at waveforms unless your test finds a failure. This blog jumps straight to waves!
I would start from the whole design first. Figure out the interfaces. Then try to express those interfaces in terms of transactions.
In fact, maybe don't even start writing VHDL as an expression of the design. Most times in industry we design via documents first. Docs express how the HW will work at a high level and how it will be verified. It breaks the design down into modules. It explains the interfaces between modules. These interfaces become possible points for the verification to look at. The test bench compares the simulated result with a golden reference when it sees a transaction event at the interface and reports a mismatch.
The point is create project infrastructure first via planning. Have a big picture view of how it's all going to be thoroughly tested automatically each time new code is committed. In industry on top of directed tests, we use constrained randomized tests. We have to determine whether we have covered everything. So we need functional coverage. All this is designed first BEFORE we play around with flops.
We can tolerate a lot of craptastic VHDL/Verilog code in industry because at the higher levels it looks neat and tidy and it is all tested vigorously.
Basically don't follow any stuff from academia because I would bet those guys have never delivered a commercial product. Educational material from tools guys is almost as bad for similar reasons. No one can hold your hand so you have to use your brain.
I probably vented too much here. It's just tough to see engineering done badly.