This is extremely cool, I've played with FPGA design but never really even looked into custom ASIC design due to budget concerns. I hadn't heard of the tinytapeout project. Any recommended links for getting started?
I have a (really dumb, kinda meme-y) project involving a dead hakko soldering iron and "Internet of Soldering", a custom ASIC for the actual front-end would be the appropriate level of silly and possibly could fit in the project budget.
As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" (https://talesonthewire.com/projects/until_heat_death_do_us_p...) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :)
> So for everyone else also running multiple instances of experimental hardware on their local network I have added an additional 2 Byte magic number using the all so original 0xCAFE (little endian) allowing packet parsers to distinguish between this ASIC’s experimental traffic and your other experimental traffic.
Just saying, it's good form to do network stuff in big endian. Although since it's already done I dunno how hard you should work to retcon that to 0xFECA...
Thanks for the pointers, hopefully I get some time to get started in that project soon!
Although I should point out that you missed the opportunity tor making the world's slowest counter and avoiding needing any expensive memory. Just declock it to an extreme degree. Hard to debug a design that never outputs anything for literal eons though.
You could easily drop the clock to 32kHz but that only saves 10 bits out of nearly 400. Getting to 1Hz requires increasing amounts of analog circuitry and only saves 26 bits. Going many powers of 2 slower starts to require counters inside your clock, so now you're replacing expensive integrated bits with much more expensive discrete logic bits.
So, since clocking low can't save you many bits, might as well give it enough bits to handle any clock up to the limits of your transistors.
The tiny tapeout project doesn't really fix the economics either. There's the obvious IO bottleneck, but worse than that, a 1000 LUT FPGA fits bigger designs and costs almost nothing. Like $2.50/FPGA at 1000 units.
Great project & article. Beyond the use of verilog, I couldn't find a description of the EDA stack. What tooling is used for the physical stages of design: place & route, LVS, DRC, and electrical circuit simulation (SPICE)?
You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects.
Also how much you can fit really depends on the node the shuttle is targeting.
So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm.
On the other hand the gates are much slower than on Skywater 130nm.
Hopefully both programs will be around for a while, so if you are still interested when you have more time you can join the shuttle then.
Nice, thanks for posting the link.
For the people unfamiliar with the Tiny Tapeout program: everyone that gets a copy of the Tiny Tapeout chip will be getting a copy of all the ASICs on the shuttle.
That memory constraint is a real killer on the chip, even one that is a first generation toy like this. Only having 4 entries in the forwarding table is going to be an immediate problem if that switch is ever connected to another switch.
I wonder if it wouldn't make sense for one of the ports to be designated the "uplink" port and if the switch receives a packet destined for something not in the table it forwards it out the uplink port so long as the packet did not arrive via that port. It could even save a bit of memory by not storing entries for the uplink port in the table.
Sure, but at that point you're just building a complicated hub, and trying to actually operate it at speed would result in most packages getting dropped due to collisions as it is pretending to be full-duplex while actually only being half-duplex.
There isn't really a restriction that a downstream device will only have one mac address.
It might be another switch. Even if it's not; VM/container networking is often implemented by bridging the host's NIC to a virtual switch, exposing the MAC addresses of all VMs/containers to the network.
I had a Google interview collapse because the last interviewer was a Principle Engineer who just couldn’t accept that a switch will ever forward a frame before reading in full and checking the FCS.
I was too much of an idiot to go along with it and instead ended up having an argument with him.
Cut-through is applicable in a minority of scenarios which are sometimes common. The majority of switches, especially the ones that support any advanced features at all, can't use it. Even when you can use it, you still can't use it all the time because of port conflicts.
As far as advanced features go, even adding and removing VLAN tags is a headache in a cut-through switch.
As far as advanced features go, even adding and removing VLAN tags is a headache in a cut-through switch.
Not really; it just needs to inject the tag right after the source address, or not pass it through at all; and of course recompute throughout and replace the FCS at the end. Other more advanced packet editing can be done in a streaming fashion too, with the latency only limited by the length of any "forward references" needed.
But "just recompute the FCS" isn't quite the right approach, is it?
With a traditional cut-through switch the entire packet is passed as-is, so you're not modifying a corrupt package. You don't drop it, but the corruption is trivially detectable on the other side. If you naively recompute the FCS on transmit you essentially mark a corrupted package as valid, so you have to compute the FCS on transmit and receive, and intentionally send out the wrong FCS on transmit if you determine the receive FCS is invalid.
Sounds like they could have used you on that team.
Bad luck, but it at least you can walk away proud knowing it was not an issue with your technical skills. :)
I remember studying cut-through forwarding in a class and thinking it was obviously going to be used everywhere.
Then I was disappointed to enter the real world of networking and learn that it wasn’t actually used as often as I had been led to believe due to conflicting with higher priority features.
So the interview may have been a conflict between textbook learning and the Google engineer’s practical experience. It’s tough to encounter that conflict in interviews because you get two people talking past each other.
I'm struggling to think of any real-world networking scenario where cut-through switching for ethernet can provide any sort of benefit.
Most data-center networks are involve aggregation/spine/core switches at higher speed than TOR/leaf switches - so the packet has to be buffered.
Most every workload is going to involve port collisions (2 packets at the same time needing the same output port) - again a full buffering required (or drops and throughput reduction).
Bigger networks start using vlans, mpls, ip routing at switches, and vxlan - requiring more lookups per-packet, larger "minimum chunks of packet seen before port is determined" sizes, etc reducing the value of cut-through.
And so on.
But i also struggle to find a scenario where a principle engineer at google is refusing to accept that cut-through switches exist, but rather, was refusing to accept that the scenario they're talking through with you would ever involve an effectively deployed cut-through switch (since that's basically never).
Ethernet frame preemption has been standardized for about 10 years for ultra low latency applications. See 802.1Qbu:
"Defines a class of service for time-critical frames that requests the transmitter in a bridged Local Area Network to suspend the transmission of a non-time-critical frame, and allow for one or more time-critical frames to be transmitted. When the time-critical frames have been transmitted, the transmission of the preempted frame is resumed. A non-time-critical frame could be preempted multiple times."
> I'm struggling to think of any real-world networking scenario where cut-through switching for ethernet can provide any sort of benefit.
When it works, it reduces latency and reduces buffer memory usage a smidge. This ASIC switch can't afford to buffer any packets, so cut through is the only option... AFAIK, most ethernet switches have at least some buffer memory...
> Most data-center networks are involve aggregation/spine/core switches at higher speed than TOR/leaf switches - so the packet has to be buffered.
If you have traffic flowing within a rack, you can cut through for that where the machines attach to the TOR switch at the same speed.
If you have traffic between racks, and it goes through a spine, it likely needs to buffer at the TORs, but it could cut through at the spine.
> Most every workload is going to involve port collisions (2 packets at the same time needing the same output port) - again a full buffering required (or drops and throughput reduction).
Depends on the workload and redundancy requirements. If you want to have dual link aggregation and no loss of throughput with a single lost link, you'll upgrade line speed when link utilization is at 50%, so maybe 50% of packets could be cut through (depending on burstiness). If latency is a key driver, you may have line speed much higher than throughput and have very little utilization.
The two scenarios I can think of that definitely make use of cut-through are timekeeping systems, and HFT. The latter goes even further, where the switches at the exchange do cut-through, but also ensure the packet is broadcast to multiple ports at the exact same time. This is done so that no specific HFT firm get an advantage from being on port 10 rather than port 20. They even measure out the outgoing fibers to be the same length.
The amount of effort an exchange goes through to ensure fairness varies substantially, unfortunately. Many do have measurable and consistent /semi-consistent differences between gateways that can be attributed to network asymmetries.
> but rather, was refusing to accept that the scenario they're talking through with you would ever involve an effectively deployed cut-through switch (since that's basically never).
Nope, the argument was exactly if a cut-through switch exists or ever existed
Edit: Actually the conversation came back to me:
He asked me about the frame format. Once I drew that on the board, he asked why is the DST before the SRC. My answer was in order for the switch to start doing the lookups ASAP and that's when I mentioned that a cut-through switch can switch the packet before it even finishes receiving it.
After that we spend the rest of the interview time arguing if cut-through switches actually exist or not. Both he and I having too big of an ego to let it go..
“Arista data planes support these packet forwarding modes:
Store and forward: the switch accumulates entire packets before forwarding them.
Cut through: the switch begins forwarding frames before their reception is complete.”
I've had it happen in an interview, many years ago. I told him we'd have to agree to disagree. After I was hired, he admitted he looked it up and I was correct (some weird SQL question he asked.)
I have a (really dumb, kinda meme-y) project involving a dead hakko soldering iron and "Internet of Soldering", a custom ASIC for the actual front-end would be the appropriate level of silly and possibly could fit in the project budget.
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