This is currently a huge source of inefficiency in modern chip design.
I've worked on some of the current highest profile chip projects doing "frontend" RTL design, and at every major chip company I've worked at, and from talking with coworkers about their past experiences at other companies, the handoff-wall between RTL and PD is leaving a substantial amount of perf per power/area on the table. (like 30% I'm general)
RTL designers generally have no visibility into how their designs are getting laid out, and generally don't want to have to care. PD engineers have no visibility into the uArch and low level code details, and maybe they want to care but everything is too obfuscated in general.
So when your pins are misplaced during an early iteration, RTL will blindly add retiming to resolve timing issues and make PD happy but never check if it's actually needed. PD will slave away trying to make busted RTL work with placement and recipe adjustments rather than asking RTL for a trivial fix, etc etc.
There are a ton of small things where visibility into either side of the process would result in measurably better hardware, but the current team structures and responsibility boundaries encourage people not to care.
That final 30% or whatever takes a lot longer to obtain than the first 70%. Big teams want to ship their chip tomorrow and it needs to work. They don't want any more risk than they're already saddled with so just leave it on the table for next time. I think what you're proposing with less siloing is obviously better (it's the only way I want to work) but it's going to come with a price. There is definitely room in the tooling to help with this, and it doesn't need to involve "AI".
Fair enough, AI doesn't have to be the only solution. But I think some of the verification (at all layers in the stacks) opportunities that AI could be key to make this a reality. (Practically, you need to free up time in order to expand responsibilities without making errors.)
I agree, there are a lot of "big picture inefficiencies" that go unnoticed, which can be avoided by having visibility through the stack. Today, siloed teams are primarily focused on day-to-day execution and miss out on these.
Why is this comment dead? (Is it just the poster's alias?) This experience is common everywhere in larger organizations, and absolutely affects chip design.
I've worked on some of the current highest profile chip projects doing "frontend" RTL design, and at every major chip company I've worked at, and from talking with coworkers about their past experiences at other companies, the handoff-wall between RTL and PD is leaving a substantial amount of perf per power/area on the table. (like 30% I'm general)
RTL designers generally have no visibility into how their designs are getting laid out, and generally don't want to have to care. PD engineers have no visibility into the uArch and low level code details, and maybe they want to care but everything is too obfuscated in general.
So when your pins are misplaced during an early iteration, RTL will blindly add retiming to resolve timing issues and make PD happy but never check if it's actually needed. PD will slave away trying to make busted RTL work with placement and recipe adjustments rather than asking RTL for a trivial fix, etc etc.
There are a ton of small things where visibility into either side of the process would result in measurably better hardware, but the current team structures and responsibility boundaries encourage people not to care.