Aside the step down, the transients can be quite crazy, which might make the power consumption higher (due to load line) calibration. 48V fets would have much worse RDSon compared to lower voltage spec'd ones. So it does make sense no single smart power stage to have such transistors (presently).
There are other issues, too. 48V would fry the GPU for sure, 12V often time does not even with a single power stage failure.
In the end we are talking about a stupid design (seriously 6 conductors in parallel, no balancing, no positive preload, lag connectors, no crimping, no solder) and the attempted fix is a much more sophisticated PCB design and passives.
There are other issues, too. 48V would fry the GPU for sure, 12V often time does not even with a single power stage failure.
In the end we are talking about a stupid design (seriously 6 conductors in parallel, no balancing, no positive preload, lag connectors, no crimping, no solder) and the attempted fix is a much more sophisticated PCB design and passives.