Yep, LBAs are the primary addressing scheme in the NVMe spec, written into every single IO command. I would imagine there could be a better way, but NVMe & OS support still carries some baggage from SATA HDDs -> SATA SSDs -> NVMe SSDs.
As you mentioned, over-provisioning and other NAND flash memory health management techniques like garbage collection and wear leveling are needed for usable modern SSDs. Modern SSD controllers are complex beasts having 3-7 microprocessor cores (probably double digit core counts now with PCIe 5.0), encryption engines, power & thermal management, error correction, multiple hardware PHYs, etc.
As you mentioned, over-provisioning and other NAND flash memory health management techniques like garbage collection and wear leveling are needed for usable modern SSDs. Modern SSD controllers are complex beasts having 3-7 microprocessor cores (probably double digit core counts now with PCIe 5.0), encryption engines, power & thermal management, error correction, multiple hardware PHYs, etc.
Example product sheet: https://www.marvell.com/content/dam/marvell/en/public-collat...