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So an in-order core that is slightly faster than rocketchip in their benchmarks. That doesn't seem all that exciting, except for the vector extension, although they only support a small subset of it. Thats sounds similar to spatz [0] and given their numbers is slightly faster.

[0] https://github.com/pulp-platform/spatz



The previous DVINO was a 5-stage in-order, this Sargantana core is a 7-stage out-of-order write-back with register renaming and a non-blocking memory pipeline.

So it is not a full in-order or a full out-of-order design.


Are the vector extensions the fixed size ones or the originally proposed lanecount agnostic ones? That is the aspect of riscv i'm most excited about.




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