* RISC-V CPU: 4x 64-bit RV64GC application cores & 1x 64-bit RV64IMAC monitor/boot core
* FPGA: 23K logic elements (4-input LUT + DFF), 68 Math blocks (18×18 MACC), and 4 SerDes lanes of 12.7 Gbps.
[0] https://www.beagleboard.org/blog/2023-11-02-beaglev-fire-ann...
Get into RISC-V and design a custom “accelerator” type thing on the FPGA.
* RISC-V CPU: 4x 64-bit RV64GC application cores & 1x 64-bit RV64IMAC monitor/boot core
* FPGA: 23K logic elements (4-input LUT + DFF), 68 Math blocks (18×18 MACC), and 4 SerDes lanes of 12.7 Gbps.
[0] https://www.beagleboard.org/blog/2023-11-02-beaglev-fire-ann...