Needs a bit more proofreading but nice to read anyway.
This might need major fix
> In a 64-bit ISA, each instruction is represented using 64 bits (8 bytes).
Not as I understand it and maybe only for exotic ISAs like VLIW. For most other, CISC or RISC, I think the instruction length might be much smaller, and in some cases, x86 for example, the length of instructions is variable (one of the reasons they have a decoder). The size of the registers is 64 bits, as are the ALU operations on these registers, and the length of the words that are addressed in memory.
This might need major fix
> In a 64-bit ISA, each instruction is represented using 64 bits (8 bytes).
Not as I understand it and maybe only for exotic ISAs like VLIW. For most other, CISC or RISC, I think the instruction length might be much smaller, and in some cases, x86 for example, the length of instructions is variable (one of the reasons they have a decoder). The size of the registers is 64 bits, as are the ALU operations on these registers, and the length of the words that are addressed in memory.