One of the difficulties of open sourcing bitstream generation of an FPGA is not the fabric itself, but all of the other IPs on the chip. Things like PCIe, Ethernet, memory controllers, SerDes and whatnot are often licensed from external vendors who don't want their register maps out in the open. Some FPGA vendors give you a simulation model, but I'm pretty sure you have to sign an NDA.
Also IPs sometimes have errata in them that need to be worked around. With an FPGA, you can usually fix it in soft logic, but vendors don't like giving that out either.
For some smaller FPGAs without complex IPs, they are starting to open up their bitstream generation algorithms. Though bitstream generation is pretty trivial compared to synthesis and place & route.
Also IPs sometimes have errata in them that need to be worked around. With an FPGA, you can usually fix it in soft logic, but vendors don't like giving that out either.
For some smaller FPGAs without complex IPs, they are starting to open up their bitstream generation algorithms. Though bitstream generation is pretty trivial compared to synthesis and place & route.