It was more that leakage current (i.e. thermal issues) and velocity saturation suddenly becoming constraints on how much you could increase switching speed along with the difficulty of high frequency clock distribution. Your individual transistor switching speed is always going to be a lot faster than your clock speed because a pipeline stage has to be made up of many layers of transistors to get anything useful done (including latch the signal at the clock edge!) and each transistor will typically drive multiple others.

I was seriously considering being a chip engineer for a while and did my master's thesis on adder design.