Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

Oddly enough, some folks like doing this because of the dopamine hit of really understanding how something works. FWIW I'm that kind of person :-). But I certainly understand it isn't for everyone.

The platform I've been using to explore stuff like this is an Ultra96 board with a LimeSDR as the receiver. The Ultra96 has the Zynq Ultrascale FPGA on it. Given that USB3 latency is < 10 uSec I am guessing (hoping?) I can implement it in the Ultrascale fabric which is fed IQ data from the USB 3.1 port.



Heh I’m that kind of person too. All my free time is spend building things!


Yup, I love that feeling, I'm currently working on a software 3d renderer, I've always understood in principle how they work, but getting to actually implement one is really fun.


Afaik USB3 latency is same as USB2, uSOFs every 125us, lowest round trip 2*125us




Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: