No, need to be such a dick about it. I was frank about not being certain about this. I have read section 1.5, and I cannot see it supporting your claim. The very first sentence says:

"The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries."

Later it talks about:

"For implementations supporting only a base instruction set, ILEN is 32 bits. Implementations supporting longer instructions have larger values of ILEN."

It seems clear to me that a standard RISC-V implementation today is 32-bit fixed sized on a 32-bit boundary. There may however be support for future architectures with longer instructions. None of this suggests that a regular RISC-V implementation has to assume that instructions can be any length.

These things are not even part of the standard yet. So please, don't be such a dick about something that isn't all that clear at the moment.