1) Don't give your guests access to the DCT control registers.
2) On 15h - no obvious way. I don't know the other families.
3) Yes -- this can be verified easily. Pick up the AMD 15h BKDG, look up BankSwizzleMode. It's documented. The one oversight is that this bit is not under the Dram Controller's lock bit.
Ah yes, that too. I like the mpg on the gen2, but gen1 seems like a much less troubled car. Beyond that, the gen1 seems like a very solid well built car punching well above it's "economy car" persona.
Solid body structure, great suspension, and even at 170k miles the only rattle I have is from a plastic panel on the rear hatch which gets slammed down thousands of times in its life so I can give it some leeway.
Intel Cooper Lake - it's a 14 nm server part that fit a particular niche (4S support, VNNI/bfloat16). It was partly due to FB, but also partly to provide a platform that was larger than ICX server could / can.
The TLB bug (Errata 298, doc 41322 if you really care - while the processor was attempting to set the A/D bits in a page table entry, an L2->L3 eviction of that PTE could occur) was one of a great many things wrong with that chip.
* A number of errata (not just 298) delayed full production, sapped performance, or negatively impacted idle power. Take a look at doc 41322, DR-BA step for many samples.
* It was late and didn't achieve performance targets; it missed clock rate targets and 2 MiB L3 was insufficient.
* Intel delivered a very compelling server part (Nehalem) during the lifecycle of family 10h.
Agreed, which is why I’m worried about retpoline as it’s a rather hacky (but obviously pragmatic) solution that isn’t compatible with shadow stacks that mitigation strategies won’t be compatible with.
2) On 15h - no obvious way. I don't know the other families.
3) Yes -- this can be verified easily. Pick up the AMD 15h BKDG, look up BankSwizzleMode. It's documented. The one oversight is that this bit is not under the Dram Controller's lock bit.