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Zeihan Zeihan Zeihan Zeihan Zeihan Zeihan. Zeihan Zeihan Zeihan Zeihan Zeihan, Zeihan. Zeihan Zeihan Zeihan?

Zeihan! Zeihan Zeihan, Zeihan Zeihan Zeihan, Zeihan Zeihan Zeihan.

Zeihan Zeihan Zeihan Zeihan? Zeihan Zeihan.


Apple seen backing up an all-new Brinks truck to Stephen Elop's WindowsCE-themed garage...


If you can make it to Texas they'll buy you a one-way ticket to the coastal metropolis of your choice



^^ POTD. Roughly 50% of all US dollars in circulation were printed in 2020 and 2021 -- the status quo became simply unsustainable. On top of that add Baby Boomer retirement capital going low-risk (i.e. out of tech).

On top of the end of cheap money, add increased operating cost due to Baby Boomers leaving the work force (~400k net loss of workers), passed-down costs of reshoring supply chains, and a burgeoning energy crunch due to the war in Eurasia.

Roughly speaking, "tech" investments are riding the tip of the bullwhip here. I expect that not-yet-profitable startups are the most vulnerable, but the sea change pervades anywhere that 2023 dollars are being spent chasing payoffs that are "many" years out and even mildly at risk.


According to Peter Zeihan, France (along with Turkey & a few others) will be emergent empires of the post-globalist age. There is ample precedent for and, and for some countries, explicit codification of using commercial tech products for state ends, particularly espionage.

So a) this is not a surprising direction at all and b) this sets up a nice little pre-fertilized, fully-walled-off plot for a French omnibus tech company to explode into.


The Oracle of Davenport...


+1000


+1. DTA + Usenet = happy days


FPGAs use SRAM to store their program, while CPLDs (complex programmable logic devices) use flash. Some clever marketeers here & there will stretch this distinction but it's an established convention. The internal architecture between FPGAs and CPLDs is typically different, based on cost of memory vs. logic and typical use cases. FPGAs tend to be used for higher-capacity computations but require more life support; CPLDs tend to serve smaller, true glue logic applications, where the low config overhead (just apply power) and quicker & simpler power-up is a strong pull.

So CPLDs will have some kind of NVRAM wear-out concern, and this is almost always specified as a number of maximum erase & program cycles.


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